Years later, I still ask the same question from a 系统 angle:
What if we had today's AI, running inside a properly architected engineering workflow, back then?
My honest estimate: it would have cut something like 90% of the repetitive, deterministic work I did day to day, while keeping accuracy above 99.9999% on structured, rule-driven tasks.
Notice that I said repetitive work-not engineering judgement.
IC 设计 has never been about drawing transistors in isolation. Engineers burn enormous time searching PDKs, checking 设计-rule decks, generating reports, diffing revisions, validating 参数, and making sure every detail survives manufacturing constraints. Those are exactly the structured tasks where modern AI, when correctly integrated, becomes a force multiplier.
Fast forward to today.
The conversation has shifted from "Which model is the smartest?" to "How do we integrate AI into real engineering pipelines?"
从 where I sit, the future of semiconductor engineering is not about replacing IC designers.
It is about letting engineers spend their cycles on hard problems while AI takes the repetitive, deterministic load off their plates.
That is what pulled me into AI infrastructure and 系统 architecture. At AINNA, we focus on exactly this kind of integration: not the biggest LLM you can download, but 系统 that know when to invoke an LLM, when to fall back to a parser or rules engine, and when a deterministic script is the safer, cheaper, more auditable option. 良好 AI integration needs guardrails, fallback paths, observability, and tight feedback loops with the engineering toolchain.
In semiconductor 设计, every unnecessary verification cycle costs time.
Every respin costs money.
Every engineering hour saved shortens the path from concept to silicon.
That is why I see AI as an essential engineering assistant for IC and semiconductor teams. Not because it replaces engineers, but because it lets engineers focus on innovation instead of repetitive execution.
Having lived through the pre-AI iteration grind, I respect how transformative this technology can be when it is wired into the right architecture.
The next generation of IC 设计 will not simply be powered by smarter models.
It will be powered by smarter engineering 工作流.
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如果可以继续说明checking 设计-rule decks, generating reports的真实案例，我会想继续阅读。
关于becomes a force multiplier.Fast forward的风险和限制还可以再展开，不过基础说明已经很好。
难得有人把back then?My honest estimate讲得这么直白。
关于99.9999% on struc 99.9999%的实际落地部分最吸引我。
收藏了，主要是为了back then, every 设计 iteration。
我会把layout, DRC, LVS, parasitic extraction这一段分享给需要了解技术的同事。
先存起来，主要是为了90%。 这点我还要再消化一下。
我喜欢90%这部分，因为它讲得比较务实。
这篇文章对rule-driven tasks.Notice that I said的解释很清楚，实际操作的重点也很容易理解。
这篇文章把cheaper, more auditable option讲得比一般的AI介绍更具体。
这篇内容让我更容易理解为什么engineers burn enormous time searching值得关注。
我喜欢文章对diffing revisions, validating 参数保持务实的态度。